The conventional Dynamic Random Access Memory (DRAM) module usually includes an on-die termination (ODT), which is used for impedance matching of signal lines and reduces signal distortion. Conventional ODTs are typically coupled to a reference voltage, such as a ground voltage. In the existing memory, when the controller performs a read operation, the ODT will be turned on first, so that voltage levels of the data signal pin DQ/DQS/DQS # of DDR3/LPDDR2/LPDDR3 stays at ½VDD, a voltage level of DDR4 stays at VDD, and a voltage level of LPDDR4 stays at VSS. When the ODT is turned on, an instantaneous current will be driven simultaneously, causing a voltage of an in-chip power supply node or a voltage of an in-chip ground node unstable.
Specifically, since a package power supply inductance exists between an external power supply node and the in-chip power supply node, and a package grounding inductance exists between an external ground node and the in-chip ground node, a voltage difference may be shown as following equations (1) and (2):V−V′=Lp(di/dt)  Eq.(1)G′−G=Lg(di/dt)  Eq.(2)
Where V is a voltage level of the external power supply node, V′ is a voltage level of the in-chip power supply node, G is a voltage level of the external ground node, G′ is a voltage level of the in-chip ground node, Lp is a package power supply inductance, Lg is a package grounding inductance, i is the current, and t is the time. As can be seen from the above, when the ODT is turned on, the voltage of the in-chip power supply node or the voltage of the in-chip ground node will be unstable due to the package power supply inductance and the package grounding inductance, which affects an operation of the memory module.
Therefore, providing a method to reduce ripple voltages of the in-chip power supply node or the in-chip ground node through the improvement of the design of the ODT circuit control mechanism, has become one of the important issues in the art.